• 专利附录
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    • 专利摘要:
    end. The technical field to which the invention described in the claims belongs A method and apparatus for converting a grayscale image into a binary image. I. The technical problem to be solved by the invention An isolation point removal method and apparatus for removing an isolation point appearing in a binary image when binarizing a grayscale image are provided. All. Summary of Solution of the Invention In the processing window having a predetermined size pixel area centered on the pixel of interest for the binary image, the connection state of the pixel of interest and the pixels adjacent thereto is irradiated for each preset irradiation pattern to generate connection information for each irradiation pattern. do. Among the pieces of connection information, the connection information indicating the connection state around the isolated point confirming region set corresponding to the isolated point size to be removed centering on the pixel of interest is checked to determine the connectivity between the isolated point confirming region and the surrounding pixels. At this time, if the pixel of interest is a "black" pixel and the isolated point checking region is determined to be unconnected with the surroundings, the pixel of interest is replaced with a "white" pixel to remove the isolated point. la. Important uses of the invention It is used to convert a gradation image into a binary image.
    公开号:KR19990032768A
    申请号:KR1019970053910
    申请日:1997-10-21
    公开日:1999-05-15
    发明作者:김행환
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Method and device for removing isolated point of binary image
    The present invention relates to an image processing apparatus, and more particularly, to a method and apparatus for converting a gray-scale image into a binary image.
    Typically, an image processing apparatus employed in a facsimile, scanner, digital copier, or the like converts an analog image signal obtained by scanning a document into digital data and processes the same. At this time, the analog image signal is converted into image data having a gray level corresponding to the document image for each pixel. For example, when the gray level of 256 levels is used, each pixel is represented by 8 bits. Therefore, the digitally converted grayscale image has a large amount of data. Accordingly, the amount of data has been drastically reduced by binarizing grayscale images and converting them into binary images. The binarized binary image is used to interpret the image, store or transmit the image, or print the image. There are various algorithms for the binarization, but basically "white" pixels according to the gray level value of the target pixel, that is, the density of the target pixel with respect to the threshold value. Convert to "black" pixels. At this time, the "white" pixel and the "black" pixel are represented by 1 bit of "1" and "0". The pixel of interest is a pixel to be currently processed.
    On the other hand, when the gray level image is binarized, unwanted speckles appear in the binary image. The isolated point is a black point that is not connected to any of the surrounding points, and a part to be expressed in white is a part expressed in black. As described above, when the gray level image is binarized, an isolation point appears in the binary image, thereby degrading the image quality of the binary image.
    As described above, when the grayscale image is binarized, there is a problem that the image quality is degraded due to the isolation point appearing in the binary image.
    Accordingly, an object of the present invention is to provide an isolation point removal method and apparatus capable of removing an isolation point appearing in a binary image when the grayscale image is binarized.
    1 is a block diagram of an isolation point removing device according to an embodiment of the present invention;
    2 is a detailed circuit diagram of a data shifter according to an embodiment of the present invention;
    3A to 3C are detailed circuit diagrams of a connection state inspection unit according to an embodiment of the present invention;
    4 is a detailed circuit diagram of the irradiation block of FIGS. 3A to 3C according to an embodiment of the present invention;
    5 is a detailed configuration diagram of the connectivity determination unit according to an embodiment of the present invention;
    6 is a detailed circuit diagram of the first determination unit of FIG. 5 according to an embodiment of the present invention;
    7 is a detailed circuit diagram of the second determination unit of FIG. 5 according to an embodiment of the present invention;
    8 is a detailed circuit diagram of the third determination unit of FIG. 5 according to an embodiment of the present invention;
    9 is a detailed circuit diagram of the fourth determination unit of FIG. 5 according to an embodiment of the present invention;
    10 is a detailed circuit diagram of the isolation point removing unit of FIG. 1 according to an embodiment of the present invention;
    11 illustrates a processing window according to an embodiment of the present invention;
    12A and 12C are exemplary diagrams showing positions in a processing window of reference pixels for setting an irradiation window according to an embodiment of the present invention;
    13A to 13L illustrate exemplary irradiation windows of the irradiation blocks of FIGS. 3A to 3C according to an embodiment of the present invention;
    14 is a view showing an irradiation window position with respect to a reference pixel in a processing window according to an embodiment of the present invention;
    15A and 15B are views illustrating irradiation ranges of the first and second irradiation modes according to an embodiment of the present invention;
    16A and 16B are diagrams illustrating 2 × 1 isolation point checks according to an embodiment of the present invention;
    17 is a view illustrating a 1 × 1 isolation point according to an embodiment of the present invention.
    The present invention for achieving the above object is irradiated pattern by irradiating the connection state of the pixel of interest and the pixels adjacent to it in a processing window having a predetermined size pixel area centered on the pixel of interest with respect to the binary image for each preset irradiation pattern Isolation point checking area by generating connection information indicating each connection state and checking the connection information indicating the connection state around an isolation point checking area that is set corresponding to the size of the isolation point to be removed around the pixel of interest among the connection information. Determine the connectivity between the pixel and the surrounding pixels, and replace the pixel of interest with the "white" pixel to remove the isolated point when the pixel of interest is determined to be a "black" pixel and the isolated point identification region is unconnected to the surroundings. .
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention, such as specific circuit configurations, components, window sizes, and the like. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.
    Figure 1 shows a block diagram of an isolation point removing device according to an embodiment of the present invention. Referring to FIG. 1, a data shifter 10 inputs parallel pixel data in a vertical scan direction of a binary image in parallel and shifts them in a horizontal scan direction. The connection state inspecting unit 12 inputs pixel data from the data shifter 10 and irradiates the connection state of the pixel of interest and the pixels adjacent thereto in a processing window having a predetermined pixel area centered on the pixel of interest for each preset irradiation pattern. To generate connection information indicating a connection state for each irradiation pattern. The connectivity determination unit 14 checks the connection information indicating the connection state around the isolation point checking area that is set corresponding to the size of the isolation point to be removed centering on the pixel of interest among the connection information of the connection state inspection unit 12. The connectivity between the verification area and the surrounding pixels is determined. At this time, the connectivity determining unit 14 determines that the boundaries of the isolated point checking area are all unconnected when all the "white" pixels are present. The isolated point removing unit 16 inputs pixel data of the pixel of interest from the data shifter 10 and "backs" the pixel of interest when the pixel of interest is a "black" pixel and is determined to be unconnected by the connectivity determining unit 14. "Replace the pixel to eliminate the isolation point.
    As described above, the data shifter 10, the connection state inspection unit 12, and the connectivity determination unit 14 of the isolation point removing device shown in FIG. 1 are configured to correspond to the size of the isolation point to be removed. Up to 3 × 3 points, i.e. 1 × 1, 1 × 2, 2 × 1, 2 × 2, 2 × 3, 1 × 3, 3 × 2, 3 × 1, 3 × 3 The example which selects and removes is demonstrated. Here, the n × m form means a pixel area having a size of (number of pixels n in the horizontal scan direction) × (pixel m in the vertical scan direction). Further, in the binary image, it is assumed that the pixel value "1" represents "white" pixel and "0" represents "black" pixel.
    In order to remove the isolation point having a maximum size of 3 × 3, a processing window of size 7 × 5 as shown in FIG. 11 is required. In Fig. 11, P0 to P4 represent five pixels that are continuous in the horizontal scanning direction, L1 to L7 represent seven pixels that are continuous in the vertical scanning direction, and x is the pixel of interest to be processed currently and is isolated by judging whether it is an isolated point. A dot indicates a pixel to be removed.
    FIG. 2 is a detailed circuit diagram of the data shifter 10 of FIG. 1 according to an embodiment of the present invention for setting the above-described 7 × 5 processing window, and includes 28 D type flip-flops 18 to 72. Configure. The data shifter 10 shown in FIG. 2 inputs seven pixel data SRDI [0..7] which are continuous in the vertical scanning direction of the binary image in parallel and shifts each of the four stages in the horizontal scanning direction for the binary image. The pixel data in the 7x4 pixel area is output based on the pixel of interest. First, 28 flip-flops 18 to 72 are initialized to the initialization signal INIT. Thereafter, the seven flip-flops 18 to 30 respectively input parallel pixel data SRDI [0..7] by one pixel and latch them by the clock signal CLK. The outputs L [1..7] P0 of the seven flip-flops 18-30 correspond to seven pixels of the first column in the horizontal scan direction in the 7 × 5 processing window of FIG. The seven flip-flops 32 to 44 to be connected are inputted and latched by the clock signal CLK and shifted by one pixel in the horizontal scan direction. The outputs L [0..7] P1 of the seven flip-flops 32 to 44 correspond to seven pixels of the second column in the horizontal scan direction in the 7 × 5 processing window of FIG. The seven flip-flops 46 to 58 to be connected are inputted and latched by the clock signal CLK and shifted by one pixel in the horizontal scan direction. The outputs L [0..7] P2 of the seven flip-flops 46 to 58 correspond to seven pixels of the third column in the horizontal scan direction in the 7 × 5 processing window of FIG. The seven flip-flops 60 to 72 to be connected are inputted and latched by the clock signal CLK and shifted by one pixel in the horizontal scan direction. The outputs L [0..7] P3 of the seven flip-flops 60 to 72 correspond to seven pixels of the fourth column in the horizontal scan direction in the 7x5 processing window of FIG. The 28 pixel data L [1..7] P [0..3] output from the 28 flip-flops 18 to 72, that is, the pixel data of the 7 × 4 pixel area, are output from the data shifter 10. Is applied to the connection state irradiation unit 12, and L4P2, which is a pixel of interest, is also applied to the isolation point removing unit 16.
    Here, the outputs L1P [0..3] of the four flip-flops 18, 32, 46, and 60 correspond to four pixels of the first row in the vertical scan direction in the 7 × 5 processing window of FIG. The output L2P [0..3] of the two flip-flops 20, 34, 48 and 62 correspond to four pixels of the second row in the vertical scan direction in the 7x5 processing window of FIG. The outputs L3P [0..3] of the flops 22, 36, 50, and 64 correspond to four pixels of the third row in the vertical scan direction in the 7x5 processing window of FIG. The output L4P [0..3] of (24, 38, 52, 64) corresponds to four pixels of the fourth row in the vertical scan direction in the 7x5 processing window of FIG. 11, and four flip-flops 26 The output L5P [0..3] of, 40,54,68 corresponds to four pixels of the fifth row in the vertical scan direction in the 7 × 5 processing window of FIG. 11, and four flip-flops (28,42). Outputs L6P [0..3] are four of the sixth row in the vertical scan direction in the 7 × 5 processing window of FIG. Corresponding to the pixel, the output L7P [0..3] of the four flip-flops 30, 44, 58, 72 is applied to the four pixels of the seventh row in the vertical scan direction in the 7x5 processing window of FIG. Yes.
    Here, although the 7 × 5 processing window of FIG. 11 is required to remove the isolation point having the maximum 3 × 3 size, the data shifter 10 of FIG. 2 does not shift once more in the horizontal scanning direction. Only 7x4 size pixel data was output. This is because, as will be described later, in the embodiment of the present invention, the connection state irradiation unit 12 uses the output delayed by one pixel in the horizontal scanning direction. This simplifies the hardware. Of course, the data shifter 10 may be configured to output pixel data of a 7 × 5 processing window using seven more flip-flops, as shown in FIG. 2.
    3A to 3C are detailed circuit diagrams of the connection state inspection unit 12 according to the embodiment of the present invention, and are composed of twelve first to twelfth irradiation blocks 74 to 96. The configuration of the connection state inspection unit 12 shown in FIGS. 3A to 3C shows an example of the case where the isolation point having the maximum size of 3 × 3 can be removed as described above. Therefore, the connection state irradiation unit 12, which is composed of the first to twelfth irradiation blocks 74 to 96 shown in FIGS. 3A to 3C, sets 3 × 3 irradiation windows based on each pixel of interest and pixels adjacent thereto. Each of the irradiation windows is irradiated for each of the irradiation patterns, as described below, for the connection state of the pixels to the surrounding pixels in the corresponding irradiation window. Here, the positions of the reference pixels for setting the irradiation window in the processing window shown in FIG. 11 are shown in FIGS. 12A to 12C. If the irradiation window of each of the first to twelfth irradiation blocks 74 to 96 of Figs. 3A to 3C is shown, it is the same as that of Figs. 13A to 13L.
    13A to 13D are irradiation windows based on two pixels L3P1 and L3P2 among the three pixels L3P1, L3P2, and L3P3 indicated by the point area in FIG. 12A. FIG. 13A is an illumination window of the first irradiation block 74, which consists of nine pixels of upper left 3x3 with L3P2 as the reference pixel x. FIG. 13B is an illumination window of the second irradiation block 76, which is composed of nine pixels of upper right 3x3 having L3P1 as the reference pixel x. FIG. 13C shows nine pixels of lower left 3x3 with L3P2 as the reference pixel x as the irradiation window of the third irradiation block 78. FIG. 13D is an illumination window of the fourth irradiation block 80, which is composed of nine pixels of lower right 3x3 having L3P1 as the reference pixel x.
    13E to 13H are irradiation windows based on two pixels L4P1 and L4P2 among the three pixels L4P1, L4P2, and L4P3 indicated by the point regions in FIG. 12B. FIG. 13E is the irradiation window of the fifth irradiation block 82, which consists of nine pixels of the upper left 3x3 with L4P2 as the reference pixel x. FIG. 13F is an illumination window of the sixth irradiation block 84, which is composed of nine pixels of the right top 3x3 having L4P1 as the reference pixel x. FIG. 13G is an irradiation window of the seventh irradiation block 86, which consists of nine pixels of lower left 3x3 with L4P2 as the reference pixel x. FIG. 13H is the irradiation window of the eighth irradiation block 88, which consists of nine pixels of the lower right 3x3 having L4P1 as the reference pixel x.
    13I to 13L are irradiation windows based on two pixels L5P1 and L5P2 among the three pixels L5P1, L5P2, and L5P3 indicated by the point regions in FIG. 12C. FIG. 13I is an illumination window of the ninth irradiation block 90, which consists of nine pixels of upper left 3x3 with L5P2 as the reference pixel x. FIG. 13J is an illumination window of the tenth irradiation block 92, which is composed of nine pixels of the upper right 3x3 having L5P1 as the reference pixel x. FIG. 13K is an illumination window of the eleventh irradiation block 94, which is composed of nine pixels of lower left 3x3 with L5P2 as the reference pixel x. Fig. 13L is the irradiation window of the twelfth irradiation block 96, which consists of nine pixels of the lower right 3x3 with L5P1 as the reference pixel x.
    Here, the upper right and lower right irradiation windows based on L3P2 in FIG. 12A and the upper left, lower left, and irradiation windows based on L3P3, the remaining one of the three pixels L3P1, L3P2 and L3P3 in FIG. 12A, are required. However, in the embodiment of the present invention, the output state obtained by delaying the connection state irradiated by the first to fourth irradiation blocks 74 to 80 along the irradiation window of FIGS. 13A to 13D in the horizontal scan direction as described later. It can be omitted because it is used. This simplifies the hardware. Of course, you may separately configure the irradiation blocks corresponding to these. This also applies to FIGS. 12B and 12C.
    On the other hand, the position of the irradiation window shown in FIG. 13A to FIG. 13L as described above is shown in FIG. 14E for the example of FIG. 13E showing the irradiation window of the fifth irradiation block 82 as shown in FIG. Referring to FIG. 14, L4P2 is referred to as the reference pixel x, and the reference pixels x and the upper left eight pixels L2P0, L2P1, L2P2, L3P0, L3P1, L3P2, L4P0, and L4P1 are respectively aa, ab, bb, ah, a, and b. , hh, and h correspond to each other to form a 3x3 irradiation window. The irradiation windows of the remaining first to fourth and sixth to twelfth irradiation blocks 74 to 80 and 84 to 96 are configured in the same manner. Therefore, description thereof is omitted.
    The first to twelfth irradiation blocks 74 to 96 all have the same configuration, and thus the input and output terminals are the same, except that the input and the output are different. First, the input terminals of each of the first to twelfth irradiation blocks 74 to 96 correspond to the nine input terminals aa, ab, bb, and ah corresponding to the 3x3 pixels constituting the irradiation window according to the same reference numerals. , a, b, hh, h, x, and an input terminal Crn and a clock terminal CLK for selecting the irradiation mode as described later. The output terminals of the first to twelfth irradiation blocks 74 to 96 each include UL, UL1, UL12, UL21, b_x_h, ULD, UL1D, UL12D, UL21D, and b_x_hD. Reference numerals ULD, UL1D, UL12D, UL21D, and b_x_hD with "D" added after the reference numerals of these output terminals respectively output the UL, UL1, UL12, UL21, b_x_h output in the horizontal scan direction by one pixel. The output is delayed.
    Among the outputs L [1..7] P [0..3] of the data shifter 10 as shown in FIG. 2, nine input terminals aa of each of the first to twelfth investigation blocks 74 to 96 are provided. Tables 1A, 3B, 3B, 3A, 3B, and 3A, 3B, and 3C show ab, bb, ah, a, b, hh, h and x.
    4 is a detailed circuit diagram of the first to twelfth irradiation blocks 74 to 96 as described above, that is, the irradiation blocks shown in FIGS. 3A to 3C according to the embodiment of the present invention, and all are configured in the same manner. The configuration shown in FIG. 4 shows an example in which the isolation point having a maximum size of 3 × 3 can be removed as described above, and any one of the first and second irradiation modes is selected. As shown in FIG. 15A, the first irradiation mode is an irradiation mode in which the connected state is irradiated to four neighboring pixels of up, down, left, and right around the reference pixel x. That is, the first irradiation mode is a mode for checking whether only up, down, left, and right points are connected with respect to one point, and in FIG. 15A, all of the top, bottom, left, and right are “white” pixels, and the reference pixel x Here is an example that is not connected at all. As shown in FIG. 15B, the second irradiation mode is an irradiation mode in which the connected state is irradiated to eight nearby pixels including up, down, left, and right as well as corners around the reference pixel x. That is, the second irradiation mode is a mode for investigating whether four corners are connected up, down, left, and right with respect to one point. FIG. 15B illustrates that the upper, lower, left, right, and corners are all “back” pixels. The example shows no connection with the reference pixel x.
    The irradiation mode is selected by the irradiation mode selection signal Crn input to the input terminal Crn, for example, to be selected by the user in software. Fig. 4 shows the configuration when the irradiation mode selection signal Crn is operated in the first irradiation mode when inputted to " 0 " and in the second irradiation mode when inputted to " 1 ". In addition, in FIG. 4, connection information indicating connection states irradiated with different irradiation patterns are output from the output terminals UL, UL1, UL12, UL21, b_x_h and their respective delayed output terminals ULD, UL1D, UL12D, UL21D, and b_x_hD.
    Firstly, the pixels aa, ab, bb, ah, a, b, hh, h constituting the irradiation window of FIGS. 13A to 13L described above with respect to the irradiation pattern of the output terminals UL21 and UL21D and the connection information generated accordingly. Look at x. In addition to x being input to the AND gate AND1, Crn is inverted, the output of b and the AND gate AND1 are input to the OR gate OR1, and to the OR gate OR2. ah is input and Crn is inverted, the outputs of the oragates OR1 and OR2 are input to the AND gate AND2, a and hh are input to the AND gate AND3, and the AND gates AND2, The output of AND3 is input to the AND gate AND4. The output of the AND gate AND4 is output to UL21 and is delayed by one pixel by the clock signal CLK in the D-type flip-flop 98 and output to UL21D.
    Therefore, UL21 and UL21D are outputted as "1" when both a and hh are "white" pixels and b or x are "white" pixels when the first irradiation mode in which the irradiation mode selection signal Crn is input as "0", Otherwise, the output is "0". On the other hand, in the second irradiation mode in which the irradiation mode selection signal Crn is input as "1", if hh, ah, a, b are all "white" pixels, they are output as "1", otherwise they are output as "0". .
    Secondly, the pixels aa, ab, bb, ah, a, b, hh, h constituting the irradiation window shown in FIGS. 13A to 13L described above with respect to the irradiation pattern of the output terminals UL12 and UL12D and the connection information generated accordingly. Look at x. Cr is inputted to the AND gate AND5 and Crn is inverted, h and the output of the AND gate AND5 are input to the OR gate OR3, ab is input to the OR gate OR4, and Crn is inverted. Input, outputs of the OR gates OR3 and OR4 are input to the AND gate AND6, a and bb are input to the AND gate AND7, and outputs of the AND gates AND6 and AND7 are connected to the AND gate (AND6). AND8). The output of the AND gate AND8 is output to UL12 and is delayed by one pixel by the clock signal CLK in the D-type flip-flop 100 and output to UL12D.
    Therefore, UL12 and UL12D are outputted as "1" when a and bb are both "white" pixels and h or x are "white" pixels when the first irradiation mode in which the irradiation mode selection signal Crn is input as "0", Otherwise, the output is "0". On the other hand, in the second irradiation mode in which the irradiation mode selection signal Crn is input as "1", it is output as "1" if h, a, ab and bb are all "white" pixels, otherwise it is output as "0". .
    Thirdly, the pixels aa, ab, bb, ah, a, b, hh, h constituting the irradiation window as shown in FIGS. 13A to 13L described above with respect to the irradiation pattern of the output terminals UL1 and UL1D and the connection information generated accordingly. Look at x. A and x are input to the OR gate OR5, Crn is inverted, and b and h are input to the AND gate AND9, and the outputs of the OR gate OR5 and AND9 are AND gate AND10. ) Is entered. The output of the AND gate AND10 is output to UL1 and is delayed by one pixel by the clock signal CLK in the D-type flip-flop 102 and output to UL2D.
    Therefore, UL1 and UL1D are outputted as "1" when both h and b are "white" pixels when the irradiation mode selection signal Crn is input as "0", otherwise it is output as "0". On the other hand, in the second irradiation mode in which the irradiation mode selection signal Crn is input as "1", if both h and b are "white" pixels and a or x is "white" pixels, it is output as "1", otherwise " The output is 0 ".
    Fourth, the pixels aa, ab, bb, ah, a, b, hh, h constituting the irradiation window as shown in FIGS. 13A to 13L described above with respect to the irradiation pattern of the output terminals UL1 and UL1D and the connection information generated accordingly. Look at x. A and aa are input to the OR gate OR6, Crn is inverted, and ab and ah are input to the AND gate AND11, and the outputs of the OR gate OR6 and the AND gate AND11 are AND gate AND12. ) Is entered. Ab is input to the OR gate OR7 and Crn is inverted, the outputs of a and bb and the OR gate OR7 are input to the AND gate AND13, and a and b are input to the AND gate AND14. The outputs of the AND gates AND13 and AND14 are input to the oragate OR8. Ah is input to the OR gate OR9, Crn is inverted, the output of hh and a and the OR gate OR9 is input to the AND gate AND15, and a and h are input to the AND gate AND16. The outputs of the AND gates AND15 and AND16 are input to the oragate OR10. The outputs of the OR gates OR8 and OR10 are input to the AND gate AND17, and the outputs of UL1 and the AND gate AND17, which are outputs of the AND gate AND10, are input to the OR gate OR11. A and b are input to the AND gate AND18, b is input to the AND gate AND19, Crn is inverted, and the outputs of bb and the AND gates AND18 and AND19 are input to the OR gate OR12. do. h and a are input to the AND gate AND20, h is input to the AND gate AND21, Crn is inverted, and hh and the outputs of the AND gates AND20 and AND21 are input to the OR gate OR13. do. The outputs of the AND gate AND12 and the OR gates OR12 and OR13 are input to the AND gate AND22, and the outputs of the ORG gate OR11 and AND22 AND22 are input to the ORG gate OR14. b and bb are input to the OR gate OR15, h and hh are input to the OR gate OR16, the outputs of the OR gates OR15 and OR16 are input to the AND gate AND23, and the AND gate 23 And the output of the OR gate OR14 are input to the AND gate AND24. The output of the AND gate AND24 is output as UL, and is delayed by one pixel by the clock signal CLK in the D-type flip-flop 104 and output as ULD.
    Therefore, when UL and ULD are the first irradiation mode in which the irradiation mode selection signal Crn is input to "0", b or bb are "white" pixels, and h or hh are "white" pixels, and in one of three cases: If it is, it is output as "1", otherwise it is output as "0". In the first case, h is a "white" pixel, h and a are both "white" pixels, hh is a "white" pixel, b is a "white" pixel, b and a are both "white" pixels, or bb is "white". "Pixels," where ah and ab are both "white" pixels. The second case is where both a and h are "white" pixels, a and hh are both "white" pixels, a and b are both "white" pixels, and a and bb are both "white" pixels. The third case is where both h and b are "white" pixels. On the other hand, in the second irradiation mode in which the irradiation mode selection signal Crn is input as "1", if b or bb are "white" pixels and h or hh are "white" pixels, and one of the following three cases is applied, " 1 ", otherwise" 0 ". In the first case, both h and a are "white" pixels, hh is "white" pixels, b and a are both "white" pixels, bb is "white" pixels, and ah and ab are both "white" pixels If a or aa is a "white" pixel. In the second case, both a and h are "white" pixels, a, hh, ah are both "white" pixels, a and b are both "white" pixels, and a, bb, ab are both "white" pixels. to be. The third case is where both h and b are "white" pixels and a or x is "white" pixels.
    Fifth, the pixels aa, ab, bb, ah, a, b, hh, h constituting the irradiation window of FIGS. 13A to 13L described above with respect to the irradiation pattern of the output terminals b_x_h and b_x_hD and the connection information generated accordingly Look at x. In addition to x being input to the OR gate OR17, Crn is inverted and the outputs of b and h and the OR gate OR17 are input to the AND gate AND25. The output of the AND gate AND25 is output as b_x_h and is delayed by one pixel by the clock signal CLK in the D-type flip-flop 106 and output as b_x_hD.
    Therefore, b_x_h and b_x_hD are output as "1" when both b and h are "white" pixels when the first irradiation mode in which the irradiation mode selection signal Crn is input as "0", otherwise is output as "0". In the second irradiation mode in which the irradiation mode selection signal Crn is input as "1", if b, h, x are all "white" pixels, it is output as "1", otherwise it is output as "0".
    Although the first to twelfth irradiation blocks 74 to 96 having outputs as described above have the same configuration, the input pixels are different from each other, so the outputs of the first to twelfth irradiation blocks 74 to 96 are respectively different. Connection information indicating a connection state for different unique irradiation patterns. The designers confirm in advance the case where the boundary points of each of the isolated point confirming areas that can be variously set, that is, the isolated point confirming areas corresponding to various sizes of the isolated point to be removed can be identified. Set it.
    The outputs of the first to twelfth irradiation blocks 74 to 96 are applied to the connectivity determining unit 14. As described above, in the case where the isolation point having the maximum size of 3 × 3 can be removed, all the outputs are It is not used in the connectivity determining unit 14 but uses only some of the required outputs. 3A to 3C, the output terminals UL, UL1, UL12, UL21, b_x_h, and ULD are used for outputs that are not used when the connectivity determining unit 14 can remove the isolation point having a maximum size of 3 × 3. , UL1D, UL12D, UL21D, b_x_hD are indicated by " x ". Among the outputs of the first to twelfth irradiation blocks 74 to 96, the outputs used by the connectivity determining unit 14 configured as shown in FIG. 5 according to the embodiment of the present invention are the same as those of FIGS. 3A to 3C. Likewise, different reference numerals have been written in consideration of the shape and position of the survey pattern to distinguish them from each other. The relationship between the output terminals UL, UL1, UL12, UL21, b_x_h, ULD, UL1D, UL12D, UL21D, and b_x_hD of the first to twelfth irradiation blocks 74 to 96 are summarized in Table 2 below. It was. In the following Table 2, "x" indicates that the outputs are not used when the connectivity determination unit 14 removes the maximum 3x3 size of the isolation point as shown in FIGS. 3a to 3c.
    As described above, the first to twelfth irradiation blocks 74 to 96 have the same configuration, while the inputs are different and the outputs are selectively used. To avoid having to configure each separately. Of course, if necessary, the first to twelfth irradiation blocks 74 to 96 may be separately configured.
    5 is a detailed configuration diagram of the connectivity determining unit 14 according to the embodiment of the present invention, and includes first to fourth decision units 108 to 114 and an OR gate OR18. The connectivity determination unit 14 is connected to the connection state inspection unit 12 and according to the size selection signals DEL 3X, DEL 3Y, DEL 2x2, DEL 3X, DEL 2x1, DEL 1x2, DEL 1x1, 1 × 1, 1 × 2. , 2x1, 2x2, 2x3, 1x3, 3x2, 3x1, or 3x3 size. The isolation point size to be removed is, for example, software-selected by the user, and the size selection signals DEL 3X, DEL 3Y, DEL 2x2, DEL 2x1, DEL 1x2, and DEL 1x1 correspond to the selected isolation point size. To the determination unit 14.
    Table 3 shows the logic states of the size selection signals DEL 3X, DEL 3Y, DEL 2x2, DEL 2x1, DEL 1x2, and DEL 1x1 according to the isolated point size to be removed as described above.
    6 shows a detailed circuit diagram of the first determination unit 108 according to the embodiment of the present invention. In FIG. 6, the size selection signal DEL 3Y is input to the AND gate AND26, and input to UL5, UR5, LR5, and LL5 from the connection state inspection unit 12 of FIGS. 3A to 3C, and the AND gate AND27. In addition to the size selection signal DEL 3Y is input, UL4, UR4, LR4, LL4 is input from the connection state inspection unit 12 of FIGS. 3A to 3C, and the size selection signal DEL 3Y is input to the AND gate AND28. In addition, UL3, UR3, LR3, and LL3 are input from the connection state inspection unit 12 of FIGS. 3A to 3C. The D type flip-flop 116 delays the output of the AND gate AND26 by one pixel by the clock signal CLK, and the D type flip-flop 118 delays the output of the D type flip-flop 116 by the clock signal CLK. Delay by 1 pixel. The D-type flip-flop 120 delays the output of the AND gate AND27 by one pixel by the clock signal CLK, and the D-type flip-flop 122 delays the output of the D-type flip-flop 120 by the clock signal CLK. Delay by 1 pixel. The D-type flip-flop 124 delays the output of the AND gate AND28 by one pixel by the clock signal CLK, and the D-type flip-flop 126 delays the output of the D-type flip-flop 124 by the clock signal CLK. Delay by 1 pixel. The output of the AND gate AND27 and the D-type flip-flops 116 to 124 is input to the OR gate OR18, and the output of the OR gate OR18 and the size selection signal DEL 3X are input to the AND gate AND29. . The output of the AND gate AND29 is output to Bx33Side, which is one of the outputs of the first determination unit 108.
    In addition, b_x_d5 is inverted from the connection state inspecting unit 12 of FIGS. 3A to 3C and the output of the AND gate AND26 is input to the AND gate AND30. B_x_h5 is input to the D-type flip-flop 128 from the connection state inspection unit 12 of FIGS. 3A to 3C and is delayed by one pixel by the clock signal CLK, and the D-type flip-flop 130 is a D-type flip-flop 128 ) Is delayed by one pixel by the clock signal CLK. An output of the AND gate AND28 is input to the AND gate AND31, and an output of the D type flip-flop 130 is inverted. The output of the AND gate AND28 is inputted to the AND gate AND32 from the connection state inspecting unit 12 of FIGS. 3A to 3C. The f_x_h3 is input to the D-type flip-flop 134 from the connection state inspection unit 12 of FIGS. 3A to 3C and is delayed by one pixel by the clock signal CLK, and the D-type flip-flop 132 is the D-type flip-flop 134. ) Is delayed by one pixel by the clock signal CLK. The output of the AND gate AND28 is input to the AND gate AND33, and the output of the D-type flip-flop 132 is inverted. The outputs of the AND gates AND30 to AND33 are input to the OR gate OR19, and the output of the OR gate OR19 and the size selection signal DEL 3X are input to the AND gate AND34. The output of the AND gate AND34 is output to Box33Crn, which is one of the outputs of the first determination unit 108.
    The first judging unit 108 as described above determines the connectivity to the isolated point checking area for removing the 3 × 3 sized isolated point. This first determination unit 108 is enabled when the size selection signals DEL 3X and DEL 3Y are both “1” as shown in Table 3 above. In addition, when the boundaries of the 3 × 3 isolated point checking region are all white pixels, a logic “1” indicating an unconnected state is output. In the first irradiation mode, Bx33Side, an output of the AND gate AND29, is output. In the case of outputting the logic "1 " and in the second irradiation mode, Box33Crn, the output of the AND gate AND34, is output as the logic " 1 ".
    7 shows a detailed circuit diagram of the second determination unit 110 according to an embodiment of the present invention. In FIG. 7, the size selection signals DEL 3x3 and DEL 2x2 are input to the AND gate AND35, and UL4 and UR4 are input from the connection state inspecting unit 12 of FIGS. 3A to 3C. The output of the AND gate AND35 is input to the AND gate AND36, and UL3 and UR21 are input from the connection state inspecting unit 12 of FIGS. 3A to 3C. The output of the AND gate AND37 is input to the D-type flip-flop 136 and delayed by one pixel by the clock signal CLK. The AND gate AND37 inputs the output of the AND gate AND35 and inputs LR3 and LL21 from the connection state inspecting unit 12 of FIGS. 3A to 3C. The D-type flip-flop 138 delays the output of the AND gate AND38 by one pixel by the clock signal CLK, and the D-type flip-flop 140 delays the output of the D-type flip-flop 138 by the clock signal CLK. Delay by 1 pixel. The AND gate AND39 inputs the size selection signals DEL 3X and DEL 2x2, and also inputs the LR4 and LL4 from the connection state inspecting unit 12 of FIGS. 3A to 3C. The output of the AND gate AND39 is input to the AND gate AND40, and UL4 and UR21 are input from the connection state inspecting unit 12 of FIGS. 3A to 3C. The outputs of the AND gates AND36 and AND40 and the D-type flip-flops 136 and 140 are input to the oragate OR20.
    In addition, the output of the AND gate AND39 is input to the AND gate AND41, and UR5 is input from the connection state inspecting unit 12 of FIGS. 3A to 3C. The output of the AND gate AND37 is input to the D-type flip-flop 136 and delayed by one pixel by the clock signal CLK. The AND gate AND42 inputs the output of the AND gate AND39 and inputs LR5 and LL21 from the connection state inspecting unit 12 of FIGS. 3A to 3C. The D-type flip-flop 144 delays the output of the AND gate AND42 by one pixel by the clock signal CLK, and the D-type flip-flop 146 delays the output of the D-type flip-flop 142 by the clock signal CLK. Delay by 1 pixel. The AND gate AND43 inputs the size selection signal DEL 3X and also inputs LR21, LL21, UR21, and UL21 from the connection state inspecting unit 12 of FIGS. 3A to 3C. The output of the AND gate AND43 is input to the D-type flip-flop 148 and delayed by one pixel by the clock signal CLK. The D-type flip-flop 150 outputs the output of the D-type flip-flop 148 to the clock signal CLK. Delays by one pixel. The output of the AND gate AND43 and the D type flip-flops 146 to 150 are input to the oragate OR21. The outputs of the oragates OR20 and OR21 are input to the oragate OR22. Box32_31, which is an output of the second decision unit 110, which is an output of the oragate OR22, becomes.
    The second determination unit 110 as described above determines the connectivity to the isolated point checking region for removing the isolated points of 3x2 and 3x1 sizes. When the size selection signal DEL 2x2 and the DEL 3X are both "1", the second determination unit 110 may set the size selection signal DEL 2x2 to "1" and the size selection signal DEL 3X to "0", as shown in Table 3 above. Is enabled when. At this time, when the size selection signals DEL 2x2 and DEL 3X are both "1", the connectivity to the isolated point confirming region for removing the isolated point of size 3x2 is determined. On the other hand, when the magnitude selection signal DEL 2x2 is "1" and the magnitude selection signal DEL 3X is "0", the connectivity to the isolation point confirmation region for removing the isolation point of size 3x1 is determined. At this time, the output Box32_31 is output as a logic "1" indicating an unconnected state only when the boundaries of the isolated point checking region having the size of 3x2 or 3x1 are all white pixels.
    8 shows a detailed circuit diagram of the third decision unit 112 according to the embodiment of the present invention. In FIG. 8, the size selection signal DEL 2x2 is input to the AND gate AND44, and UL5, UR12, UR5e1, and LL5 are input from the connection state inspecting unit 12 of FIGS. 3A to 3C. The LL5 is delayed by one pixel by the clock signal CLK in the D type flip-flop 152 and input to the AND gate AND45 together with UL12, UR5, and LR5. The size selection signal DEL 2x2 is input to the AND gate AND46, and UL4, UR4e1, LR4e1, and LL4 are input, and the output of the AND gate AND46 is one pixel by the clock signal CLK in the D-type flip-flop 154. Delay. The outputs of the AND gates AND44 to AND46 and the D-type flip-flop 154 are input to the OR gate OR23. The size selection signal DEL 2x2 is input to the AND gate AND47, and UL3, UR3e1, LR12, and LL3 are inputted, and the UL3 is delayed by one pixel by the clock signal CLK in the D-type flip-flop 156, so that the AND gate ( AND48) is input together with UR3, LR3, and LL12. UL1, UR1, LR12L5, and LL12L5 are input to the AND gate AND49, and UL12L3, UR12L3, LR1, and LL1 are input to the AND gate AND50. The outputs of the AND gates AND49 and AND50 are input to the OR gate OR26, and the output of the OR gate OR26 and the size selection signal DEL 3Y are input to the AND gate AND51. UL1L3, UR1L3, LR12L4, and LL12L4 are input to the AND gate AND52. Outputs of the AND gates AND47, AND48, AND51, and52 are input to the oragate OR24. The outputs of the OR gates OR23 and OR24 are input to the OR gate OR25, and the output of the OR gate OR25 is input to the AND gate AND53 together with the size selection signal DEL 3Y. The output of the AND gate AND53 is delayed by one pixel by the clock signal CLK in the D type flip-flop 162 and output to Box23_13, which is one of the outputs of the third decision unit 112.
    In addition, UL5, UR1, LR4e1, and LL4 are input to the AND gate AND55, and the LL4 is delayed by one pixel by the clock signal CLK in the D-type flip-flop 158, so that UL1, UR5, and LR4 are connected to the AND gate AND54. Is entered together. The outputs of the AND gates AND54 and AND55 are input to the OR gate OR27, and the output of the OR gate OR27 is input to the AND gate AND56 together with the size selection signal DEL 3Y. The output of the AND gate AND56 is output to Box22f which is one of the outputs of the third decision unit 112. The D-type flip-flop 160 delays UL4 by one pixel by the clock signal CLK, and the output of the D-type flip-flop 160 is input to the AND gate AND57 together with UR4, LR3, and LL1. UL4, UR4e1, LR1, and LL3 are input to the AND gate AND58, and the outputs of the AND gates AND57 and AND58 are input to the AND gate AND59 together with the size selection signal DEL 3Y. The output of the AND gate AND59 is output to Box22b which is one of the outputs of the third decision unit 112.
    The third decision unit 112 as described above determines the connectivity to the isolated point checking area for removing isolated points of 2x2, 2x3, and 1x3 sizes. This third decision unit 112 is enabled when at least one of them is "1" as shown in Table 3 above. At this time, when only the size selection signal DEL 2x2 is "1", the connectivity to the isolated point confirming region for removing the isolated point of size 2x2 is determined. On the other hand, when both the size selection signal DEL 2 × 2 and the size selection signal DEL 3Y are “1”, the connectivity to the isolation point checking area for removing the 2 × 3 size isolation point is determined. When only the size selection signal DEL 3Y is "1", the connectivity to the isolated point confirming region for removing the 1 x 3 isolated point is determined. At this time, the output Box23_13 is output as a logic " 1 " indicating the unconnected state only when the boundaries of the isolated point confirming areas of 2x2, 2x3, or 1x3 are all white pixels. Box22f and Box22b, which are outputs of the AND gates AND56 and AND59, are output to the fourth decision unit 114 and used.
    9 shows a detailed circuit diagram of the fourth decision unit 114 according to the embodiment of the present invention. In FIG. 9, UL21, UR1, LR1, and LL21 are input to the AND gate AND60, UL1, UR21, LR21, and LL1 are input to the AND gate AND60, and the outputs of the AND gates AND60 and AND61 are OR. The output of the OR gate OR29 is input to the AND gate AND62 together with the size selection signal DEL 2x1. UL1L3, UR1L3, LR1, and LL1 are input to the AND gate AND63, UL1, UR1, LR1L5, and LL1L5 are input to the AND gate AND64, and the outputs of the AND gates AND63 and AND64 are the ORGATE OR30. The output of the OR gate OR30 is input to the AND gate AND65 together with the size selection signal DEL 1 × 2. The outputs of the AND gates AND62 and AND65 are input to the oragate OR31 along with Box22f and Box22b which are outputs of the third decision unit 112. UL1, UR1, LR1, and LL1 are input to the AND gate AND66, and the output of the AND gate AND66 is input to the AND gate AND67 together with the size selection signal DEL 1x1. The outputs of the OR gate OR31 and the AND gate AND67 are input to the OR gate OR32, and the output of the OR gate OR32 is delayed by one pixel in the D-type flip-flop 164 by the clock signal CLK. It is output to W22 which is the output of the 4th determination part 112.
    The fourth decision unit 114 as described above determines the connectivity to the isolated point checking area for removing isolated points of 1 × 1, 1 × 2, and 2 × 1 sizes. This fourth decision unit 114 is enabled when at least one of them is "1" as shown in Table 3 above. At this time, when the size selection signal DEL 2x1 is "1", the connectivity to the isolated point confirming region for removing the isolated point of size 2x1 is determined. On the other hand, when the size selection signal DEL 1 × 2 is " 1 ", the connectivity to the isolated point confirming region for removing the 1 × 2 isolated point is determined. When the size selection signal DEL 1 × 1 is " 1 ", the connectivity to the isolated point confirming region for removing the 1 × 1 sized isolation point is determined. At this time, the output W22 is output as a logic " 1 " indicating an unconnected state only when the boundaries of the isolated point confirming regions of 1x1, 1x2, or 2x1 size are all white pixels.
    The outputs of the first to fourth decision units 108 to 114 as described above are input to the oragate OR18, and the output of the oragate OR18 is the finality determination of the connectivity determination unit 14. It is applied to the isolation point removal unit 16 as a.
    FIG. 10 is a detailed circuit diagram of the isolation point removing unit 16 of FIG. 1 according to an exemplary embodiment of the present invention, and includes an oragate OR33 and a D-type flip-flop 166. The OR gate OR33 inputs the connectivity determination signal BSD from the connectivity determination unit 14, and inputs the pixel of interest L4P3 from the data shifter 10, and the D-type flip-flop 166 outputs the OR gate OR33. Latch to output. If the pixel of interest L4P3 is not the isolation point, the connectivity determination signal BSD becomes a logic "0", so that the pixel of interest L3P4 is output as it is to the output of the isolation point removal unit 16. That is, in the isolated point removing unit 16, when the pixel of interest L4P3 is not the isolated point, the actual pixel of interest L4P3 is output as it is. On the other hand, when the pixel of interest L4P3 is an isolated point, the connectivity determination signal BSD becomes a logic "1", so that the output of the isolated point removal unit 16 is also output to a logic "1" which is a white pixel. That is, in the isolated point removing unit 16, the pixel of interest L4P3 is replaced with a logic " 1 " which is a white pixel instead of the actual pixel of interest L4P3 value in the case of the isolated point. As a result, a binary image with the isolated point removed is output.
    Therefore, when the gray level image is binarized, the isolation point appearing in the binary image appearing in the binary image can be removed. In addition, the isolation point size to be removed can be variably selected as needed, and the irradiation mode can be selected for various purposes.
    For example, the case of removing the 2 × 1 isolation point is described as follows. When viewed from the 7 × 5 processing window, the area around the two points of L4P1 and L4P2 in FIG. 16A and around the two points of L4P2 and L4P3 in FIG. 16B are checked to determine whether the surrounding is white. That is, two points of L4P1 and L4P2 of FIG. 16A and two points of L4P2 and L4P3 of FIG. 16B become an isolated point confirmation area. In the following description, it is assumed that only 4 neighborhoods of the first irradiation mode, that is, the upper, lower, left, and right sides, are examined.
    To determine the connection state of the isolated point confirming areas of FIGS. 16A and 16B as described above, the connection information obtained by the fifth to eighth check blocks 82 to 88 of FIG. 3B is used. 16A, first, it is checked whether L4P0, L3P1, and L3P2 are all "white" pixels by UL21 of the fifth irradiation block 82, and L3P2 and L4P3 are "white" by UL1D of the sixth irradiation block 84. Whether L4P0, L5P1, L5P2 are "white" pixels by UL21 of the seventh irradiation block 86, and whether L5P2 and L4P3 are "white" pixels by UL1D of the eighth irradiation block 88 Investigate. Combining the above, it can be seen whether or not the value around two points in FIG. 16A is a "white" pixel.
    In a similar manner, Fig. 16B is also examined. Investigate whether L4P1 and L3P2 are "white" pixels by UL1 of the first irradiation block 82, and whether L3P2, L3P3 and L4P4 values are all "white" pixels by UL21D of the second irradiation block 84, The UL1 of the seventh irradiation block 86 checks whether L4P1 and L5P2 are "white" pixels, and the UL21D of the eighth irradiation block 88 determines whether the values of L5P2, L5P3 and L4P4 are "white" pixels. have. Examining both cases can determine whether the desired 2x1 point is an isolated point.
    In other cases, we can find out whether each size is an isolated point by looking for conditions that can cover whether or not the points of each size are "white" pixels.
    As another example, if the 1 × 1 isolation point is removed, the connectivity determination determines the connectivity around the pixel of interest X as shown in FIG.
    Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, the embodiment of the present invention showed an example of selectively removing the size of the isolated point up to a size of 3 × 3, this size can be changed as necessary. In this case, the size of the processing window and the irradiation window may be set corresponding to the maximum size of the isolation point to be removed, and the connection state irradiation unit and the connectivity determination unit may be configured correspondingly. In addition, we have given an example that allows us to choose either the size of the isolation point or the irradiation mode to be removed, but it may be possible to apply only one fixedly or to vary the number of selectable gadgets as needed. Similarly, the irradiation pattern can be set differently as long as the boundary points of each of the isolated point checking areas can be identified. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalent of claims and claims.
    As described above, the present invention has an advantage of preventing deterioration in image quality by removing the isolation point appearing in the binary image when the grayscale image is binarized.
    权利要求:
    Claims (18)
    [1" claim-type="Currently amended] In the method for removing the isolated point appearing in the binary image when the grayscale image is binarized,
    Setting a processing window having a pixel area of a predetermined size around the pixel of interest for the binary image;
    Generating connection information indicating a connection state of each irradiation pattern by irradiating the connection state of the pixel of interest and the pixels adjacent thereto within the processing window for each preset irradiation pattern;
    Determining connectivity between the isolated point confirming region and surrounding pixels by checking connection information indicating a connection state around an isolated point confirming region set corresponding to an isolated point size to be removed centering on the pixel of interest among the connection information; Process,
    And removing the isolated point by replacing the pixel of interest with a “white” pixel when the pixel of interest is a “black” pixel and the isolated point checking region is determined to be unconnected with the surroundings. How to remove the dots.
    [2" claim-type="Currently amended] The method of claim 1, wherein the generating process comprises setting irradiation windows of a predetermined size based on the pixel of interest and each of the pixels adjacent to the pixel of interest, and for each of the irradiation windows to the surrounding pixels of the pixels in the corresponding irradiation window. And removing the connection point for each of the irradiation patterns.
    [3" claim-type="Currently amended] The method of claim 1, wherein the disconnected state is a state in which all of the boundaries of the isolated point confirming region are "white" pixels.
    [4" claim-type="Currently amended] The method of claim 1, wherein the isolated point confirming area is a pixel area having a predetermined size selected from among various sizes of the isolated point to be removed.
    [5" claim-type="Currently amended] The method of claim 4, wherein the irradiation patterns are configured to identify all boundary points of each of the isolated point confirming regions corresponding to various sizes of the isolated point to be removed.
    [6" claim-type="Currently amended] The method of claim 4, wherein the size of the irradiation window is set to correspond to the maximum size of the isolation point to be removed.
    [7" claim-type="Currently amended] An apparatus for removing an isolation point appearing in a binary image when binarizing a grayscale image,
    A data shifter which inputs the pixel data consecutive in the vertical scan direction of the binary image in parallel and shifts them in the horizontal scan direction, respectively;
    The pixel state is input from the data shifter, and the connection state of the pixel of interest and the pixels adjacent thereto is irradiated for each preset irradiation pattern in a processing window having a predetermined pixel area centered on the pixel of interest. A connection state research unit generating connection information indicating
    Determining connectivity between the isolated point confirming region and surrounding pixels by checking connection information indicating a connection state around an isolated point confirming region set corresponding to an isolated point size to be removed centering on the pixel of interest among the connection information; Connectivity determination unit,
    An isolation point removal unit for removing the isolation point by replacing the pixel of interest with a "white" pixel when the pixel of interest is a "black" pixel and determined to be unconnected by the connectivity determination unit. Point remover.
    [8" claim-type="Currently amended] 8. The pixels of claim 7, wherein the connection state irradiation unit sets irradiation windows of a predetermined size based on the pixel of interest and each of the pixels adjacent thereto, and surrounds the pixels in the corresponding irradiation window with respect to each of the irradiation windows. The isolation point removing device, characterized in that for irradiating the connection state for each irradiation pattern.
    [9" claim-type="Currently amended] The isolation point removing apparatus according to claim 7, wherein the connectivity determination unit determines that the connection state is not connected when all of the boundaries of the isolation point confirming region are "white" pixels.
    [10" claim-type="Currently amended] The isolation point removing apparatus according to claim 7, wherein the isolation point confirming region is a pixel region having a predetermined size selected from one of various sizes of the isolation point to be removed.
    [11" claim-type="Currently amended] The apparatus of claim 10, wherein the irradiation patterns are configured to identify all boundary points of each of the isolated point confirming regions corresponding to various sizes of the isolated point to be removed.
    [12" claim-type="Currently amended] The apparatus of claim 10, wherein the size of the irradiation window is set to correspond to a maximum size of the isolation point to be removed.
    [13" claim-type="Currently amended] An apparatus for removing an isolation point appearing in a binary image when binarizing a grayscale image,
    Input seven pixel data consecutively in the vertical scanning direction of the binary image in parallel and shift the pixel data in a 7 × 4 pixel area with respect to the pixel of interest for the binary image by shifting each of the four levels in the horizontal scanning direction. With a data shifter
    Input the pixel data from the data shifter to check the connection state of the pixel of interest and the pixels adjacent thereto for each preset irradiation pattern in a processing window having a 7 × 5 pixel area centered on the pixel of interest. A connection state research unit generating connection information indicating
    Among the connection information, the connection information indicating the connection state around the isolated point confirming region, which is set up to 3 × 3, corresponding to the isolated point size to be removed centering on the pixel of interest, is checked. A connectivity determination unit that determines the connectivity between them,
    An isolation point removal unit for removing the isolation point by replacing the pixel of interest with a "white" pixel when the pixel of interest is a "black" pixel and determined to be unconnected by the connectivity determination unit. Point remover.
    [14" claim-type="Currently amended] The pixel of claim 13, wherein the connection state irradiation unit sets 3 × 3 irradiation windows based on the pixel of interest and each of the pixels adjacent thereto, and surrounds the pixels in the corresponding irradiation window with respect to each of the irradiation windows. The isolation point removing device, characterized in that for irradiating the connection state for each irradiation pattern.
    [15" claim-type="Currently amended] 15. The irradiation mode according to claim 14, wherein the connection state irradiation unit is one of a first irradiation mode for irradiating the connected state to four neighboring pixels and the second irradiation mode for irradiating eight neighboring pixels with respect to the reference pixel. The isolation point removal device, characterized in that selected as.
    [16" claim-type="Currently amended] The isolation point removal apparatus according to claim 13, wherein the connectivity determination unit determines that the connection state is not connected when all of the boundaries of the isolation point confirmation region are "white" pixels.
    [17" claim-type="Currently amended] The method of claim 13, wherein the isolated point confirming area is one of 1 × 1, 1 × 2, 2 × 1, 2 × 2, 2 × 3, 1 × 3, 3 × 2, 3 × 1, and 3 × 3 sizes. An isolated point removing device, characterized in that selected to correspond to the size of the isolated point to be removed of any one size.
    [18" claim-type="Currently amended] 18. The apparatus of claim 17, wherein the irradiation patterns are configured to identify all boundary points of each of the isolated point confirming areas corresponding to various sizes of the isolated point to be removed.
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    同族专利:
    公开号 | 公开日
    KR100265883B1|2000-09-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1997-10-21|Application filed by 윤종용, 삼성전자 주식회사
    1997-10-21|Priority to KR1019970053910A
    1999-05-15|Publication of KR19990032768A
    2000-09-15|Application granted
    2000-09-15|Publication of KR100265883B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019970053910A|KR100265883B1|1997-10-21|1997-10-21|Method and device for removing speckle of binary image|
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